1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More specifically, the present invention is directed to a dynamic random access memory (DRAM) cell capacitor.
2. Description of Background Art
For more than three decades, there has been a steady miniaturization of device dimensions being used for integrated circuit technology. As the chip density of memory cells increase, the area available for a capacitor of a DRAM storage cell (i.e., storage node) shrinks.
A relatively large capacitance is required for a high signal-to-noise ratio in a sense amplifier, and for the reduction of the soft errors due to alpha particle interference. Therefore there is a desire to reduce the cell dimension and yet retain a high capacitance, thereby achieving both high cell integration and reliable operation.
For example, it is known in the semiconductor manufacturing industry that the capacitance of a cell capacitor, even in the gigabit storage range, should be at least 30 femto-farad. One approach for increasing the capacitance while maintaining high-density integration of the storage cells is directed toward the shape of the capacitor electrode. In this approach, the polysilicon layer implementing the capacitor electrode can have protrusions, fins, cavities, etc., to increase the capacitance while maintaining the small area occupied on the substrate surface.
For example, Fazan et al., in U.S. Pat. No. 5,278,091, describe a capacitor over bit line (COB) storage node featuring a hemispherical grained (HSG) polysilicon layer on the storage node, which provides increased surface area.
However, as the chip density increases beyond the gigabit range and the minimum feature size approaches the 0.1 :m scale, it is likely that one will observe a bridge problem between the adjacent storage nodes in a DRAM cell capacitor. Since a bridge between the adjacent storage nodes can cause twin-bit and multi-bit failures in the manufacture of high-density DRAMs, it is crucial to resolve the bridge phenomena before the implementation of a stacked capacitor. In the case of a xe2x80x9cbox-typexe2x80x9d stacked capacitor, increasing the distance between the adjacent storage nodes can alleviate the bridge problem. Increasing inter cell distance, however, defeats minimization.
Recently, a capacitor structure named xe2x80x9cconcave structurexe2x80x9d has been proposed in an effort to resolve the above-mentioned bridge problem. The concave structure employs a sacrificial oxide to implement a cylindrical capacitor. A method of manufacturing the concave cylindrical capacitor is disclosed in a technical paper entitled, xe2x80x9cA New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs,xe2x80x9d by S. P. Sim, et al., published in the Technical Digest of International Electron Device Meeting (IEDM), pp. 597-600, 1996.
FIGS. 1A to 1D are schematic cross-sectional views illustrating various manufacturing steps for a traditional concave cell capacitor.
The prior art, as disclosed in FIGS. 1A-1D and 2A-2D, shows a method of manufacturing the concave cylindrical capacitor. The manufacturing method comprises providing an activation layer 56 having isolation elements 55 that define active regions 53; forming a contact pad 58 in electrical connection with active regions 53; providing an insulating film 54 over the activation layer 56 and the isolating elements 55; forming storage nodes 52 within insulating film 54; forming a contact 51 by employing a sacrificial oxide layer 50; depositing a polysilicon layer 57 over the layered structure, for serving as a storage node; filling the contact hole 51 with a protective oxide 59; performing a chemical mechanical polishing (CMP) process for cell isolation and removing the sacrificial oxide layer 50 and the protection oxide 59.
The manufactured device disclosed in the prior art, however, still suffers from a xe2x80x9clift-offxe2x80x9d problem of the polysilicon layer. This is because some residue of the polysilicon layer is left on the surface of the wafer after the CMP process.
FIGS. 2A and 2B are schematic cross-sectional views illustrating the xe2x80x9clift-offxe2x80x9d problem of the polysilicon layer as it occurs in the prior art.
Referring to FIGS. 2A and 2B, some residue 60 of the polysilicon layer 57 is left on the surface of the sacrificial oxide layer 50 if the contact hole 51 is not completely open. This is called xe2x80x9cNOT OPENxe2x80x9d in the art due to the close spacing between the adjacent storage nodes 52.
Furthermore, some polysilicon patches 60 may detach from the polysilicon layer 57 and float during the CMP process. This can cause failure of the semiconductor device if the polysilicon layer sticks to the surface of the wafer. In addition, an alignment key may not be completely opened if the step height is relatively high, thereby causing similar xe2x80x9cNOT OPENxe2x80x9d problems to be observed during the step of forming a buried contact.
In this case, the floating patches 60 or the residues of the patterned polysilicon can stick to the surface of the cell area, which consequently causes failure in the manufacture of a DRAM cell capacitor.
There is a need in the art for a cell capacitor that is not subjected to the limitations of the prior art.
Accordingly, it is a feature of the present invention to provide a cell capacitor for the manufacture of a DRAM.
Another feature of the present invention is to provide a method of manufacturing a cell capacitor, which resolves the xe2x80x9clift-offxe2x80x9d problem of the polysilicon patches of the prior art.
Still another feature of the present invention is to provide a cell capacitor and a manufacturing method thereof, which resolve the xe2x80x9cNOT OPENxe2x80x9d problem of the prior art.
Still yet another feature of the present invention is to provide a cell capacitor and a manufacturing method thereof, which cures the floating problem of polysilicon patches, which detaches from the sacrificial oxide layer.
A further feature of the present invention is to provide a cell capacitor and a manufacturing method of the same, which reduces the number of lithographic stages.
Yet another feature of the present invention is to provide a cell capacitor and a manufacturing method thereof, which prevents the misalignment between a storage node and a node contact.
As a result, it becomes possible to implement a concave cell capacitor having neither the xe2x80x9cbridgexe2x80x9d nor the xe2x80x9clift-offxe2x80x9d problems of the prior art.
In accordance with a broad aspect of the present invention, provided is a method of manufacturing a cylindrical cell capacitor comprising forming a first insulating layer over a substrate, forming a first conductive layer on the first insulating layer, forming a first opening window to expose a portion of the first insulating layer by etching the first conductive layer, providing a first dielectric layer on at least an inner surface of the first opening window, forming a second conductive layer on the first dielectric layer, providing a spacer on sidewalls of the first opening window by etching the second conductive layer and first dielectric layer, forming a second opening window by etching the first insulating layer using the spacer as a mask, and forming a third conductive layer in at least the first and second opening windows to electrically connect with the substrate. Preferably, the step of forming the first opening window comprises forming a contact opening by selectively etching a portion of the second insulating layer and etching the first conductive layer using the contact opening as a mask.
The present invention further provides a method of manufacturing a cell capacitor wherein the lower electrode pattern and the lower electrode contact are simultaneously fabricated by a single photolithography step. According to an alternate embodiment of the present invention, the upper electrode of the cell capacitor is formed prior to the fabrication of the lower electrode.
In the manufacture of a cell capacitor in accordance with the present invention, a transistor having a source and drain is formed on a semiconductor substrate. A pad for a bit line is then formed on the source/drain region of the transistor. Thereafter, a first interlayer dielectric is deposited on the pad and covers the transistor. A pattern for the bit line is then formed through the first interlayer dielectric to electrically connect the pad to the bit line. A second interlayer dielectric is then formed on the first interlayer dielectric and the bit line pattern. A contact pad for the lower electrode of a cell capacitor is formed to electrically connect the source/drain region through the first and the second interlayer dielectrics. A third interlayer dielectric is formed on the contact pad and the second interlayer dielectric. Thereafter, a first conducting layer and a fourth interlayer dielectric are consecutively deposited on the third interlayer dielectric layer. A photoresist layer is then spin-coated on the fourth interlayer dielectric and patterned. Thereafter, the fourth interlayer dielectric is etched to open a window by employing the patterned photoresist layer as a mask. After eliminating the photoresist layer, the window is enlarged by wet-etching the fourth interlayer dielectric layer. The purpose of the wet etching step is to increase the surface area of the lower electrode. A trench for the lower electrode is then formed through a step of etching the first conductive layer, the purpose of which is to provide the upper electrode of a cell capacitor.
Preferably, the remaining first conductive layer, which was not eliminated in the previous etching step, will be employed as an upper electrode of a cell capacitor. Consequently, the trench patterns for the lower electrode and the upper electrode are simultaneously formed in a single photolithographic step.
The manufacturing process further includes forming a thin capacitor dielectric on the inner surface of the trench capacitor and depositing a second conductive layer on the thin capacitor dielectric for forming a spacer. Preferably, the second conductive layer is made from titanium nitride or is a stacked layer of titanium nitride and doped polysilicon. The above-mentioned second conductive layer is then anisotropically etched to form a spacer on the sidewalls of the trench. The spacer is used as a mask to open a contact opening, which exposes the underlying contact pad by etching the capacitor dielectric and the second interlayer dielectric layer. Preferably, the contact opening is formed in a self-aligned manner. A third conductive layer is then deposited in the contact opening in such a way that the trench and the contact opening will be completely filled with the third conductive layer. Finally, the third conductive layer is etched to form a cell capacitor by employing the fourth interlayer dielectric layer as a stopping layer. In this case, the fourth interlayer dielectric layer prevents electrical shortage between the upper and lower electrodes.
In a preferred embodiment of the present invention, a silicon oxynitride layer is further formed on the fourth interlayer dielectric as an anti-reflection coating (ARC) layer. In the case of employing an ARC layer, the manufacturing method of forming a trench for the lower electrode comprises forming an ARC layer on the fourth interlayer dielectric layer, forming a photoresist layer on the ARC layer, forming a contact opening through an etching step of the ARC layer, and after removing the photoresist layer patterning the fourth interlayer dielectric layer by a wet etching, employing the ARC layer as a mask. The fourth interlayer dielectric layer is etched to the side direction of the contact opening, and a first opening is formed to constitute a trench for the lower electrode of a cell capacitor by etching the first conductive layer.
In accordance with another broad aspect of the present invention, there is provided a semiconductor device comprising a substrate, a first conductive layer to electrically connect with the substrate, a first dielectric layer, a second conductive layer, wherein the first dielectric layer is formed on at least the sidewalls of the second conductive layer and the second conductive layer encloses the sidewalls of the first conductive layer.
Further features of the present invention will become apparent from a description of the fabrication process and a structure resulting therefrom, taken in conjunction with the accompanying drawings of the preferred embodiment of the invention. However, the disclosed preferred embodiments should not be taken to be limitative to the invention.